This invention relates to a method of equilibrating digit sense lines of a random access memory.
Computers and other electronic applications digitally store information. Broken down into basic building blocks of logic states, the information is stored in memory as either a xe2x80x9conexe2x80x9d or a xe2x80x9czero.xe2x80x9d DRAM (Dynamic Random Access Memory) is the predominate storage medium currently utilized. Information is stored as an electrical charge as one of these respective logic states in one of a multitude of storage cells; in this system the cell in its simplistic form is a capacitor accessed through a transistor. These storage cells are laid out in multitude of arrays in rows and columns and each is located at the intersection of a row line and a column line, which are used to access the cell. Cells along a common digit line do not share a word line, and cells along a common word line do not share a digit line.
Reading the contents of a memory cell requires not only accessing the cell through the row and column lines and associated access transistors but also determining whether the stored charge represents a one or zero. To determine the logic state of the cell, the stored charge is compared to a reference charge in a sense amplifier. If the stored charge is greater than the reference charge then the it represents a one, if it less than the reference charge it represents a zero.
Prior to accessing any memory cell, digit lines which are connectable to the sense amplifier are equilibrated to common potential. Generally, random access memory devices include equilibration circuits for this purpose. The equilibration circuit typically comprises one or more transistors that are connected between paired digit lines of two separate sub-arrays on either side of the sense amplifier. These transistors are enabled prior to accessing the memory cell to provide a common voltage on the digit lines and to short the paired digit lines together to average the charges in the two lines. A typical equilibrate voltage is Vcc/2. Typically, it is also desirable to equilibrate, or pre-charge, the sense amplifier input. The memory cell is then accessed and its charged sensed by the sense amplifier. Typically, a sense amplifier will comprise a pair of latches, each having cross coupled transistors, one uses an NMOS transistor pair and is termed the N sense amplifier, while the other latch uses a PMOS transistor pair and is termed the P sense amplifier.
FIG. 1 illustrates a conventional sense amplifier 30 containing the N and P sense amplifier and related equilibration circuitry. The sense amplifier senses a first memory array ARRAY A 20 and a second memory array ARRAY B 22, each of which contains a plurality of memory cells. Sense amplifier 30 senses the voltage level in a selected memory cell of the selected ARRAY A 20 or B 22, via the pair of complimentary digit lines DA 24 and DA* 26 or DB 25 and DB* 27, respectively. One of the arrays A 20, B 22 is selected by the application of signals to a word line 16 or 18 corresponding to a memory cell in memory ARRAY A 20 or memory ARRAY B 22, respectively and to ISOA and ISOB to transistors 32a, 32b and 34a, 34b, respectively. Thus, when ISOA is enabled and driven to a logic high value, transistors 32a and 32b become conductive, i.e., turn on, to connect ARRAY A 20 to sense amplifier 30. When ISOB is enabled and driven to a logic high value, transistors 34a and 34b turn on to connect ARRAY B 22 to sense amplifier 30.
Equilibration circuits 50 and 80 are provided to pre-charge the digit lines. For simplicity the operation of equilibrated circuit 50 for the memory ARRAY A 20 side of the sense amplifier 30 is now described, it being understood that equilibration circuit 80 operates the same way for the memory ARRAY B 22 side of the sense amplifier 30.
Equilibration circuit 50 includes transistor 54 with a first source/drain region coupled to digit line DA 24, a second source/drain region coupled to digit line DA* 26 and a gate coupled to receive an equilibration signal labeled EQA. Equilibration circuit 50 further includes transistors 56, 58 and 60. Transistor 56 includes a first source/drain region that is coupled to digit line DA 24, a gate that is coupled to receive the equilibration signal EQA, and a second source/drain region that is coupled to a first source/drain region of transistor 60. Transistor 58 includes a first source/drain region that is coupled to digit line DA* 26, a gate that is coupled to receive the equilibration signal EQA, and a second source/drain region that is coupled to the first source/drain region of transistor 60. Transistor 60 has a second source/drain region that is coupled to an equilibration voltage DVC2, typically Vcc/2, and a gate that is connected to a pumped Vcc voltage, VCCP, which is typically about one to two volts higher than Vcc. The application of VCCP to the gate of transistor 60 causes transistor 60 to supply equilibrated voltage to transistor 56, 58. When the EQA signal is at a high logic level, transistors 56, 58 apply the equilibrated voltage the digit line DA 24 and digit line DA* 26 and transistor 54 shorts the lines such that both lines are equilibrated to the voltage Vcc/2.
During a read operation, the digit line DA 24 will go to Vcc or GND depending on the stored charge in the read cell. Sense amplifier 30 senses the differential voltage across the digit lines DA 24 and DA* 26, which represents the charge stored in the accessed memory cell and drives the digit line (DA 24, DA* 26) containing the higher voltage to Vcc and the digit line (DA 24, DA* 26) containing the lower voltage to GND. These respective voltages, VCC and GND, are also provided to the I/O, I/O* lines 36, 38.
This equilibration configuration of FIG. 1 works well if there are no defects (i.e., shorted column or row lines) on any of the digit lines DA 24, DA* 26 or DB 25, DB* 27. If, however, there is a defect, such as a column to row short on a digit line on one side of sense amplifier 30, the digit lines and sense amplifier 30 will be equilibrated to a value much less than Vcc/2 (i.e., ground, in case of a hard short). This can significantly reduce or eliminate any zero""s margin for the functional side digit lines. Thus, there are problems with the conventional equilibration circuits 50 and 80 as laid out in FIG. 1 and utilized as discussed, when a column to row fabrication short circuit occurs within a memory array. For example, when a short in memory array A 20, consisting of a short between digit line DA 24 and wordline WLA 16, does occur, a conductive path is created between ground and Vcc/2 through transistors 56 and 60. Typically, transistor 60 is sized to limit the amount of current that will pass through it when a short exists. For example, the current is typically limited to approximately 40 mA. As the densities of memory circuits increase, however, the number of such column to row shorts increases. Thus, the total current drawn from Vcc/2 to ground by multiple shorts may be sufficient to cause a significant decrease in the voltage Vcc/2. A decrease in the voltage Vcc/2 will adversely affect the operation of the sense amplifier 30, as the digit lines DA 24 and DA* 26 will not be properly pre-charged. Additionally, a column to row short increases the power consumption by the memory device, and also increases the accompanying heat dissipation, both of which can adversely affect the operation of the memory device and system in which it is installed. Furthermore, a short in ARRAY A 20 can effect the equilibration of ARRAY B 22 and sense amplifier 30 and visa versa.
There have been several methods proposed to prevent such a drop in the level of Vcc/2 caused by column to row shorts. For example, a global Vcc/2 supply line with a fuse, parallel to a column select line, has been proposed. Thus, if a column to row short circuit, exists in ARRAY A 20, a fuse could be blown, thus removing the supply voltage Vcc/2 from equalization circuits 50a, 50b and preventing the short circuit from causing a decrease in the voltage Vcc/2. There are problems with this approach, however, as the opening of a fuse disables all segments in a column and will disable every segment in that column, requiring an entire redundant column for repair, instead of just a column segment to replace the defective memory cell.
Thus, there exists a need for an equilibration circuit in a memory device that limits and isolates excessive current from being drawn during equilibration so that under short conditions the sense amplifier can continue to properly read memory cells from digit lines on one side of the sense amplifier which are unaffected by shorts on the digit lines on the other side of the sense amplifier.